 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| C8051F062 25 MIPS, 64 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU Analog Peripherals Two 16-Bit ADCs High-Speed 8051 C Core - - 1.5 LSB INL; guaranteed no missing codes Programmable throughput up to 1 Msps (each ADC) Configurable as two single-ended or one differential ADC DMA to XRAM or external memory interface Data-dependent windowed interrupt generator Programmable throughput up to 200 ksps 8 external inputs Built-in temperature sensor (3 C) Can synchronize outputs to timers for jitter-free waveform generation Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler 4352 bytes data RAM 64 kB Flash; in-system programmable in 1024-byte sectors (1024 bytes are reserved) External parallel data memory interface 32 message objects "Mailbox" implementation only interrupts CPU when needed 24 port I/O; all are 5 V tolerant Hardware SMBusTM (I2CTM compatible), SPITM, and two UART serial ports available concurrently Programmable 16-bit counter array with 6 capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using timers or PCA Internal programmable 2% oscillator: up to 24.5 MHz External oscillator: Crystal, RC, C, or Clock Memory 10-Bit ADC CAN Bus 2.0B Digital Peripherals Two 12-Bit DACs Three Comparators Internal Voltage Reference Precision VDD Monitor/Brown-out Detector On-Chip JTAG Debug & Boundary Scan - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan Typical operating current: 10 mA at 25 MHz Multiple power saving sleep and shutdown modes Clock Sources 100-Pin TQFP - Temperature Range: -40 to +85 C Supply Voltage: 2.7 to 3.6 V VDD VDD VDD DGND DGND DGND AV+ AGND Digital Power Analog Power TCK TMS TDI TDO RST MONEN XTAL1 XTAL2 JTAG Logic Boundary Scan Debug HW Reset 8 0 5 1 C o r e UART0 UART1 SMBus SPI Bus PCA P0 Drv P0.0 P0.7 P1.0/AIN2.0 P1.7/AIN2.7 VDD Monitor External Oscillator Circuit 25 MHz 2% Internal Oscillator WDT SFR Bus Timers 0, 1, 2,3,4 P0, P1, P2, P3 Latches C R O S S B A R P1 Drv P2 Drv P2.0 P2.7 System Clock 64 kB FLASH 256 byte RAM 4 kB RAM P3 Drv P3.0 P3.7 CTX CRX VREF2 CAN 2.0B (32 Message Objects) VREF VREFD DAC0 DAC1 AVDD ADGND AV+ AGND VREF0 VRGND0 AIN0 AIN0G VBGAP0 CNVSTR0 VREF DAC0 (12-Bit) ADC 200 ksps (10-Bit) CP0 CP1 CP2 A M 8:1 U X + + + - Temp Sensor P2.6 P2.7 P2.2 P2.3 P2.4 P2.5 ADC0 1 Msps (16-Bit) AVDD ADGND AV+ AGND VREF1 VRGND1 AIN1 AIN1G VBGAP1 CNVSTR1 R E S U L T 0 External Data Memory Bus Bus Control P4 Latch Ctrl Latch P5 Latch Addr15-8 P6 Latch Addr7-0 P7 Latch Data Latch P4 DRV P5 DRV P6 DRV P7 DRV P4.5 P4.6 P4.7 P5.0 P5.7 P6.0 P6.7 P7.0 P7.7 ADC1 1Msps (16-Bit) R E S U L T 1 + - D I F F DMA EMIF Cntrl Address Bus Data Bus CAN 2.0B Copyright (c) 2004 by Silicon Laboratories 6.15.2004 C8051F062 25 MIPS, 64 kB Flash, 16-Bit ADC, 100-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = -40 to +85 C, VDD = 2.7 V unless otherwise specified) PARAMETER CONDITIONS GLOBAL CHARACTERISTICS Supply Voltage Supply Current (CPU Clock = 25 MHz active) Clock = 1 MHz Clock = 32 kHz; VDD Monitor Enabled Supply Current Oscillator not running; VDD Monitor (shutdown) Disabled Clock Frequency Range 16-BIT A/D CONVERTERS Resolution Integral Nonlinearity Single-ended Mode Differential Mode Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Fin = 10kHz, Single-ended Distortion Fin = 10kHz, Differential Total Harmonic Distortion Fin = 10kHz, Single-ended Fin = 10kHz, Differential Spurious-Free Dynamic Fin = 10kHz, Single-ended Range Fin = 10kHz, Differential Throughput Rate Input Voltage Range Single-ended (AINn-AINnG) Differential (AIN0-AIN1) Power Supply Current Operating Mode, 1 Msps (each ADC) (AVDD + AV+) Shutdown Mode D/A CONVERTERS Resolution Differential Nonlinearity Output Settling Time MIN 2.7 18 0.7 20 0.1 DC 16 1.5 1 0.5 86 89 96 103 97 104 0 -VREF 5.5 1 12 1 10 25 4 2 1 TYP MAX 3.6 UNITS V mA mA A A MHz bits LSB LSB LSB dB dB dB dB dB dB Msps V V mA A LSB LSB s 1 VREF VREF Package Information D D1 C8051F060DK Development Kit MIN NOM MAX (mm) (mm) (mm) A 1.20 0.15 A1 0.05 A2 0.95 1.00 1.05 b D E1 E 0.17 0.22 0.27 16.00 14.00 0.50 16.00 14.00 - D1 e E E1 100 PIN 1 DESIGNATOR 1 e A b A1 A2 CAN 2.0B Copyright (c) 2004 by Silicon Laboratories 6.15.2004 Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders |
Price & Availability of C8051F062
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |